Hardware co-simulation allows a circuit or system designer to partition an electronic circuit design into multiple pieces, and to simulate or emulate one or more of these pieces on a hardware platform. The other portions of the design are typically simulated using software models running on a host PC workstation. The hardware platform operates under the control of the host workstation, which coordinates communication and data transfers between the software and hardware portions of the design. Hardware co-simulation can be advantageous over fully software-based simulations for numerous reasons, including simulation acceleration, the availability of hardware debug, and real-time verification capabilities.
Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field, programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay-locked loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a circuit design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
PLDs are well suited for hardware co-simulation, due to their reprogrammable nature. It is common for designs to be modified frequently during development. Therefore, in many cases it is useful to be able to co-simulate an up-to-date circuit. By using a PLD as the target platform, a circuit design can be re-complied into a PLD configuration data file once changes are made, and the PLD can be reprogrammed with the new configuration file.
Some PLD companies now provide co-simulations environments that support the use of their PLDs for co-simulation. For example, the “System Generator™ for DSP” software from Xilinx, Inc., is a high-level modeling system that allows electronic designs to be assembled, simulated, and translated into FPGA hardware. System Generator for DSP provides co-simulation interfaces that support numerous FPGA platforms, e.g., the Xilinx ML402 Evaluation Platform and other platforms. In System Generator for DSP, software interfaces and drivers to the PLD hardware are encapsulated by a “run-time hardware co-simulation block”. A run-time co-simulation block functions like the other blocks in the circuit design, in that it has ports that produce and consume the same types of signals on which traditional blocks operate.
In the System Generator for DSP software, design hierarchy is supported by subsystems, or systems within other systems. A subsystem is represented as a special block in a “Simulink” diagram. Users can push into a subsystem block, which includes an additional diagram beneath it. Subsystems are used to identify the portion or portions of a design that a user wishes to co-simulate in hardware. When a particular subsystem is compiled for hardware co-simulation, everything within the subsystem is compiled into hardware resources. Once compilation is complete, a new run-time block is created that exposes the same external interface as the subsystem from which it was compiled. Additional information on how designs are compiled for hardware co-simulation can be found in the section entitled “Using FPGA Hardware in the Loop: Compiling a Model for Co-Simulation” (pages 187-189) of the “Xilinx System Generator for DSP v8.1 User's Guide” manual, which pages are hereby incorporated herein by reference. This document is dated Apr. 25, 2006, is available from Xilinx, Inc., and can also be found on the internet as of the filing date of the present patent application at: http://www.xilinx.com/support/sw_manuals/sysgen_ug.pdf.
One type of hardware co-simulation interface that has proved particularly useful is JTAG-based hardware co-simulation. JTAG hardware co-simulation allows any board with a JTAG header and a Xilinx FPGA to be used in the simulation-loop inside System Generator for DSP. To co-simulate a design, a user connects a programming cable (e.g., Platform Cable USB or Parallel Cable IV) to the JTAG header on the FPGA platform. Simulation commands and data are transmitted between the host workstation and hardware platform over the programming cable. Additional information on JTAG co-simulation can be found in the section entitled “Using FPGA Hardware in the Loop: JTAG Hardware Co-simulation” (pages 196-210) of the “Xilinx System Generator for DSP v8.1 User's Guide” manual, which pages are hereby incorporated herein by reference.
A shortcoming of the present system for co-simulation using JTAG is that the JTAG hardware co-simulation infrastructure does not support concurrent co-simulation using multiple PLDs. It is not uncommon for hardware co-simulation platforms to contain multiple PLD devices; however, JTAG co-simulation is not adequately supported for these platforms. Rather than a cohesive solution allowing concurrent co-simulation, JTAG co-simulation can only be performed using one of the PLDs at any given time.
Therefore, it is desirable to provide systems and methods enabling concurrent JTAG co-simulation of multiple PLDs in a co-simulation hardware platform.